Electrostatic discharge (ESD) events are a common part of everyday life and some of the larger discharges are detectable by the human senses. Smaller discharges go unnoticed by human senses because the ratio of discharge strength to surface area over which the discharge occurs is very small.
Integrated circuits (ICs) have been shrinking at an incredible rate over past decades. By way of example, transistors in ICs have shrunk to 32 nm and will likely continue to shrink. As transistors shrink in size, the supporting components around transistors generally shrink as well. The shrinking of IC dimensions decreases the ESD tolerance of transistors thereby increasing the sensitivity of integrated circuits to ESD stress.
An ESD event occurs when an object at a first potential comes near or into contact with an object at second potential, resulting in single event discharge. Rapid transfer of charge from the first object to second object occurs such that the two objects are at approximately equal potential. Where the object with lower charge is an IC, the discharge attempts to find the path of least resistance through the IC to a ground. Often, this path flows through interconnects. Any part of this path that is unable to withstand the energy associated with the discharge sustains damage.
Fabrication sites where the manufacturing of integrated circuits is carried out have matured and implemented procedures to prevent ESD events during manufacturing. For example, design rules assure that large charges do not accumulate during manufacturing. Conventionally, ESD protective structures are also built into the substrate and connected to the devices for protection. These structures consume a considerable amount of area (tens to hundreds of square microns for each ESD buffer) on the substrate that could otherwise be used for active circuitry.
One recent development in further advancing IC capabilities is stacking ICs to form a 3-D structure or stacked IC having multiple tiers. For example, a cache memory may be built on top of a microprocessor. The resultant stacked IC has a significantly higher density of devices, but also requires significantly more complex manufacturing methods than an individual IC.
For stacked ICs, manufacturers may create a first-tier IC at a first fabrication site and create a second-tier IC at a second fabrication site. A third fabrication or assembly site may then assemble the tiers into a stacked IC. When tiers of the ICs are bonded during die-to-die bonding at the third fabrication site they may experience an ESD event because each tier may be charged to a different potential. The magnitude of such ESD events during die-to-die bonding is unknown. Moreover, no standard procedures for handling stacked ICs have been implemented.
As a result, there is a need to measure and record values of ESD events during die-to-die bonding so that appropriate handling procedures may be developed and ESD circuitry on the stacked IC may be optimized.